ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 185

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
Preliminary
IBM Processor for Network Resources
Memory Reset Sequence
After a reset, onboard ROM or external firmware must properly configure the control registers for
COMET/PAKIT.
If using SRAM, the reset sequence is complete. If using SDRAM, bit 3 of the memory controller’s SDRAM
Command and Status Register must be written to a ’1’ to initiate forcing the SDRAMs out of the self refresh
state and performing the POR sequence. When bits five and four of this register are '00', the SDRAMs are
ready for use.
Note: Memory configuration errors occur if an attempt is made to use memory that is configured incorrectly
or, if an attempt is made to use SDRAM before the POR sequence is completed.
Accesses to the first 0x20 bytes of memory (Control or Packet) are not allowed unless bit 26 of the corre-
sponding memory control register is set. With this restriction in place, accesses with zero-valued pointers will
cause the zero address error bit in the memory controller's status register to be set.
pnr25.chapt04.01
The DRAM Controllers (COMET/PAKIT)
August 14, 2000
Page 185 of 676