ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 238

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Preliminary
Entity 8: The Bus DRAM Cache Controller (BCACH)
This entity provides the caching function for data transfers on the Control Processor bus. The array is orga-
nized in four logically separate cache lines, any of which can be used for processor accesses or master/slave
DMA accesses. The cache is accessible on byte boundaries on the Control Processor side; access of this
entity to COMET is performed on 64-bit (word) boundaries. The address tags of each of the four 32-byte
cache lines are compared to the requesting address to select the bank to be used to satisfy the Control Pro-
cessor bus operation.
Streaming accesses of the cache use a predictive look-ahead scheme to fill the cache for read operations
from Packet Memory. Under normal conditions, a single cache miss will be expected at the start of each DMA
read operation. This cache miss will initiate a read operation from Packet Memory to fetch the requested data
and enough additional data to fill the remainder of the cache line. If the requested data is in the last N bytes
(N is programmable via the BCACH control register) of the cache line, the read operation to COMET will be
extended to fill the next cache line with sequential data as well. This same programmable value is used to
determine when to initiate the next sequential cache line fill operation during a DMA read operation. During
non-aligned write operations to Packet Memory, BCACH will perform read/modify/write cycles to PAKIT.
Processor accesses operate without predictive caching. When a cache miss occurs, a COMET read opera-
tion will be initiated to fetch the 32-byte block of data that contains the requested data. The data read from
COMET will be loaded into the ‘Least Recently Used’ cache line.
This section contains descriptions of the registers used by the Bus Cache logic.
The Bus DRAM Cache Controller (BCACH)
pnr25.chapt04.01
Page 238 of 676
August 14, 2000