ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 31

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Internal Architecture
Logical Channel Support
The Logical Channel is the unit of resource allocation in ATM. At one level, the End Station negotiates with
the Network Interface to determine the characteristics of each End Station-to-End Station connection. The
resources that may be reserved in the network are defined in the ATM UNI (User Network Interface) Specifi-
cation (see references in Standards Compliance on page 23). These resources include (but are not limited to)
the peak and average bandwidth to be used by the logical channel, the maximum burst length that may be
transmitted at the burst rate, the latency and variance of the connection, and the loss probability.
The term Logical Channel rather than virtual circuit or VPI/VCI is used in this databook to provide a level of
abstraction from these specific instances.
A Switched Virtual Circuit (SVC) can be negotiated with specific characteristics specifically for it.
A virtual path can be negotiated with the
plexed, using the VCI on that single VPI, without having to renegotiate for each additional VCI. The Logical
channel, with respect to the network, would be the Virtual Path. There would be multiple logical channels
internal to the End Station based on the Virtual Circuits used within the path.
Using ATM Adaptation Layers 3 and 4, a Multiplexing IDentifier (MID) can be used to provide multiple Logical
Channels across a single VPI/VCI.
All of these Logical Channels are dealt with uniformly in IBM3206K0424. A hierarchy of Logical Channel
Descriptors can be built up, and frames or buffers can be queued to each of the LCDs. See Transmit Buffer
(CSKED) on page 273 for details.
Virtual Memory Support
The Packet Memory space appears on the bus as a group of up to 128K buffers (configurable size). A level of
indirection has been added to the addressing of Packet memory to provide these large frame buffers without
requiring memory behind all of them at the same time. This has been done for a number of reasons:
The memory does not page or swap. There are two major efficiencies used internally:
pnr25.chapt01.01
August 14, 2000
• The frames on the network can be up to 64KB long.
• The receiver does not know how long a frame will be until it is completely received.
• Software generally has a much easier time dealing with contiguous memory.
• The first N bytes of memory in a buffer are directly referenced.
• The blocks that make up the buffers are of multiple sizes.
network.
Several virtual circuits within that path can then be multi-
IBM Processor for Network Resources
Internal Architecture
IBM3206K0424
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