ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 5

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
nrm.toc.01
August 14, 2000
DMA QUEUES (DMAQS) .................................................................................................................... 154
General Purpose DMA (GPDMA) ...................................................................................................... 175
INTST CPB Capture Enable .......................................................................................................... 144
INTST CPB Captured Address ...................................................................................................... 145
INTST General Purpose Timer Pre-scaler .................................................................................... 145
INTST General Purpose Timer Compare ...................................................................................... 146
INTST General Purpose Timer Counter ........................................................................................ 146
INTST General Purpose Timer Status ........................................................................................... 147
INTST General Purpose Timer Mode Control ............................................................................... 148
INTST Enable for PCORE Normal Interrupt .................................................................................. 149
INTST Enable for PCORE Critical Interrupt ................................................................................... 149
INTST Debug States Control ......................................................................................................... 150
INTST Delayed Interrupts DMA System Address 1 ....................................................................... 152
INTST Delayed Interrupts DMA System Address 2 ....................................................................... 152
Current PCI Master Address Counter for Debug ........................................................................... 152
External Entity States Read ........................................................................................................... 153
DMA Descriptors ........................................................................................................................... 154
DMA Types and Options ............................................................................................................... 155
Descriptor Based DMAs ................................................................................................................ 156
Register Based DMAs ................................................................................................................... 156
Polling, Interrupts, or Events ......................................................................................................... 156
Error Detection and Recovery ....................................................................................................... 156
DMA/Queue Scheduling Options ................................................................................................... 156
Address Size ................................................................................................................................. 156
Data Width ..................................................................................................................................... 157
Initialization of DMAQS .................................................................................................................. 157
DMAQS Lower Bound Registers ................................................................................................... 158
DMAQS Upper Bound Registers ................................................................................................... 159
DMAQS Head Pointer Registers ................................................................................................... 160
DMAQS Tail Pointer Registers ...................................................................................................... 160
DMAQS Length Registers ............................................................................................................. 161
DMAQS Threshold Registers ........................................................................................................ 161
DMAQS Interrupt Status ................................................................................................................ 162
DMAQS Interrupt Enable ............................................................................................................... 164
DMAQS Control Register .............................................................................................................. 164
DMAQS Enqueue DMA Descriptor Primitive ................................................................................. 166
DMAQS Source Address Register ................................................................................................ 166
DMAQS Destination Address Register .......................................................................................... 167
DMAQS Buffer Address Register .................................................................................................. 167
DMAQS Transfer Count and Flag Register ................................................................................... 168
DMAQS System Descriptor Address ............................................................................................. 171
DMAQS Checksum Register ......................................................................................................... 171
DMAQS Local Descriptor Range Registers ................................................................................... 173
DMAQS Event Queue Number Register ....................................................................................... 173
DMAQS DMA Request Size Register ............................................................................................ 174
DMAQS Enq FIFO Register .......................................................................................................... 174
GPDMA Interrupt Status ................................................................................................................ 175
GPDMA Interrupt Enable ............................................................................................................... 176
GPDMA Control Register .............................................................................................................. 177
GPDMA Source Address Register ................................................................................................ 178
GPDMA Destination Address Register .......................................................................................... 179
IBM Processor for Network Resources
IBM3206K0424
Page 5