ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 127

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ibm3206k0424

Manufacturer Part Number
ibm3206k0424
Description
Ibm Processor For Network Resources
Manufacturer
ETC-unknow
Datasheet
Preliminary
1.24: Message Signaled Interrupts-Word 1
This register contains the part of the Message Signaled Interrupts structure. See bit definitions.
Length
Type
Address
Restrictions
Power on Reset Value
(Big Endian)
Power on Reset Value
(Little Endian)
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31-16
Bit(s)
15-8
7-0
Message Control
Next Pointer
Capability ID
Name
Message Control
32 bits
Read Only/Read/Write
XXXX 00C0
Cannot be written unless by Crisco, or the PCI config space override write bit is on.
X’0082D005’
X’05D08200’
See PCI spec revision 2.2 for more details. Bits 31-24 are 0, and bit 23 is 1. Bits 22-20 are
the Multiple Message Enable field, and bits 19-17 are the Multiple Message Capable field.
Bit 16 is MSI Enable. Only bits 16, 20, 21, and 22 are writable.
Pointer to the next item in the capabilities list.
Set to 05h to identify this function as Message Signaled Interrupt capable.
Next Pointer
Description
The IOP Bus Specific Interface Controller (PCINT)
IBM Processor for Network Resources
9
8
7
6
5
Capability ID
4
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IBM3206K0424
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