ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 306

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
11.2: SEGBF Control Register
This register provides a mechanism to control the various programmable features of SEGBF. See Note on
Set/Clear Type Registers on page 93 for more details on addressing.
Length
Type
Address
Power On Value
Restrictions
ATM Transmit Buffer Segmentation (SEGBF)
Page 306 of 676
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31-16
12-10
Bit(s)
9-8
6-5
15
14
13
7
4
Steer Internal Status to ENSTATE Outputs
These bits are used to steer internal SEGBF status to the ENSTATE outputs.
This bit, when set, will cause the segmentation processors to free a software enqueued buffer after the last cell has been
generated.
This bit, when set, will cause the segmentation processors to queue a transmit complete event after the last cell has been
generated for a software enqueued frame.
This bit, when set, will cause the segmentation logic to pause when it reaches the idle state. Segmentation will not be
continued until this bit has been reset. Care must be taken to leave this bit set for a very short duration so that segmenta-
tion throughput will not be adversely affected.
Reserved
These two bits define the prioritization scheme used by the segmentation logic to determine which drop to build a cell for
when running in frame mode. A value of ‘00’ will provide for equal priority among all drops, the drops will be processed in
order from zero to three as long as data is available to segment and space is available in the cell buffer for the drop. A
value of ‘01’ will provide descending priority from drop 0 to drop 3. If data exists and a cell buffer is available for drop 0, a
drop 0 cell will always be built regardless of the situation on any other drops. In this mode, a cell will only be built on drop
three if all other drops either have not data or no cell buffer available.
This bit, when set, will reset all control logic in the entity. After being set, this bit must be reset before the segmentation
logic will function properly. This bit must remain set for at least one microsecond to reset the segmentation logic properly.
These two bits define the number of cell buffers that can be filled on a given drop before a not ready condition is returned
to the cell scheduler. This addresses latency issues caused by multiple cells waiting for transmission by the lower link
level. A value of ‘00’ allows all four cell buffers to be used at any time; a value of ‘01’ allows one cell buffer to be used; a
value of ‘10’ allows two cell buffers to be used, and a value of ‘11’ allows three buffers to be used.
This bit, when set, enables the transmit complete event modification logic in the segmentation processors. This logic will
retrieve two bits from the xmit_comp_evnt_mod field in the LCD and logically OR them with bits eight down to seven of
the buffer address being enqueued to RXQUE. This logic only functions when buffer addresses are being queued; it will
not modify the event if LCD addresses are being enqueued. This also adds the restriction that all buffer addresses must
start on a 512-byte boundary or greater.
32 bits
Clear/Set
XXXX 1408 and 40C
X’98400000’
None
Description
9
8
7
6
5
4
pnr25.chapt05.01
August 14, 2000
3
Preliminary
2
1
0