ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 140

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
2.5: INTST Enable for Interrupt 1 (MINTA)
This register serves as an enable for interrupt 1. See the INTST Interrupt Source register on page 139 for the
bitwise description that the corresponding bit in this register will enable. See Note on Set/Clear Type Regis-
ters on page 93 for more details on addressing.
Length
Type
Address
Restrictions
Power on Reset value
Interrupt and Status/Control (INTST)
Page 140 of 676
Bit(s)
16
15
14
13
12
11
10
8
7
6
5
4
3
2
1
0
9
Reserved.
POOLS
CHKSM
CSKED
Reserved
SEGBF
Reserved
LINKC
Reserved
INTST GP Timer
Reserved
Reserved
PBIST
Spurious Interrupt
PCORE
External INTA
VIMEM
Name
32 bits
Clear/Set
XXXX 0418 and 1C
None
X’00000000’
Reserved.
The POOLS entity has interrupts that need handling.
The PCORE entity has User Defined interrupts that need handling.
The CHKSM entity has interrupts that need handling.
This bit will be set when the IBM3206K0424 detects that MINTA is low and, conditionally,
when the same bit in INTST Enable for PCORE Normal Interrupt or INTST Enable for
PCORE Critical Interrupt is set. This bit is for use by the PCORE entity, and it is recom-
mended that interrupts directed out which drive output (MINTA) be disabled.
The CSKED entity has interrupts that need handling.
Reserved
The SEGBF entity has interrupts that need handling.
Reserved
The LINKC entity has interrupts that need handling.
Reserved
The INTST General Purpose Timer Counter has reached the INTST General Purpose
Timer Compare value and caused an interrupt.
Reserved
The VIMEM entity has interrupts that need handling.
Reserved
This bit is set when the PBIST entity did not indicate that it was done. It is also not clear-
able.
Under normal conditions, this bit should never be set. However, if one of the other bits in
this register turns on, then off, a spurious interrupt condition will occur. The manual vector
passed to the processor will point to this bit being on.
Description
pnr25.chapt04.01
August 14, 2000
Preliminary