ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 215

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
6.17: VIMEM Real Buffer Base Addresses
These registers contain the address in Packet Memory at which a block of memory begins that is used to pro-
vide a given size buffer. In general, the block allocated must be large enough to contain as many buffers as
will be freed to POOLS on initialization. However, for Real Buffer Base 4, the size of the block reserved must
be large enough so that one buffer is available for each of the virtual buffers freed to POOLS. These buffers
must not be freed to POOLS because they are implicitly used as the first real buffer segment for each of the
virtual buffers. If a given base register (and associated buffer size) is not used, the low four bits of the register
should be set to X’F’ to ensure that accesses of this buffer size are detected and flagged as an error. When
using real memory mode (controlled in POOLS), all of these base registers are unused with the exception of
base register zero, which contains the base address for all real memory buffers. In real mode, the low four
bits of base register zero are of no significance. The size of the real buffers is controlled through the Buffer
Size Register.
Buffer Size
Length
Type
Address
Power on Value X’0020 000F’
Restrictions
pnr25.chapt04.01
August 14, 2000
Bit(s)
1-0
Defines the size of each map entry:
00
01
10
11
0
32 bits
Read/Write
XXXX 0D20
The base address for any given buffer size must begin on a boundary that is equal to the
buffer size. For example, the base address for 128-byte buffers must be on a 128-byte
boundary, and the base address for 4096-byte buffers must be on a 4096-byte boundary.
When a base register is written, the hardware performs an automatic adjustment to the
address using the contents of the Packet Memory real base register and the Packet Mem-
ory offset register. This results in the actual value being stored, not being the value that is
written by the program. This is done to make the memory accesses that use the base reg-
ister execute quicker. The reverse adjustment is made when the read operation is per-
formed, so that it appears to the program no different than a normal operation. Care must
be taken however to ensure that the Packet Memory Real Base Register and the Packet
Memory Offset Register are set-up before any of the base registers are written. If the
Packet Memory Base Register or the Packet Memory Offset Register is changed, Packet
Memory should not be accessed until all the base registers have been written again. The
power on value of these registers is actually the power on value of the Packet Memory Real
Base Register added to the contents of the Packet Memory Offset Register added to the
original contents of these registers (X'0000000F').
8 bytes
16 bytes
32 bytes
64 bytes
1
32 bits
Read/Write
XXXX 0D24
X’0020 000F’
2
32 bits
Read/Write
XXXX 0D28
X’0020 000F’
Description
IBM Processor for Network Resources
3
32 bits
Read/Write
XXXX 0D2C
X’0020 000F’
ATM Virtual Memory Logic (VIMEM)
4 (implicit)
32 bits
Read/Write
XXXX 0D30
X’0020 000F’
Page 215 of 676
IBM3206K0424