ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 167

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
3.12: DMAQS Destination Address Register
This register is used to set and keep track of the destination address during a DMA transfer. This is the Des-
tination address for the current DMA transfer. In 32-bit addressing mode, the low-order 32 bits of the register
are written, and the high-order 32 bits are reset when the register is loaded. A bit in the Transfer Count and
Flag Register determines whether the destination address is internal to the IBM3206K0424 or is a system
address.
Length
Type
Address
Power on Value
Restrictions
3.13: DMAQS Buffer Address Register
This register is used to set and keep track of the POOLS Buffer address during a DMA transfer. When the
DMA Descriptor directs that a new buffer address be obtained from POOLS, this is Buffer Address for the cur-
rent DMA transfer. A bit in the Transfer Count and Flag Register determines whether a buffer address has
been obtained for this descriptor. This register can be written to an RXQUE queue. The low-order seven bits
should be set to 0x2a, the event code for Assign Pool Buffer events.
This is the Destination address for the current DMA transfer. In 32-bit addressing mode, the low-order 32 bits
of the register are written, and the high-order 32 bits are reset when the register is loaded. A bit in the Trans-
fer Count and Flag Register determines whether the destination address is internal to the IBM3206K0424 or
is a system address.
.
Length
Type
Address
Power on Value
Restrictions
pnr25.chapt04.01
August 14, 2000
32 bits
Read/Write
Queue 0
Queue 1
Queue 2
X’0000000000000000’
None
32 bits
Read/Write
Queue 0
Queue 1
Queue 2
X'0000002a'
These registers should not be written during normal system operation.
The low-order 7 bits are set to 0x2a and should not be modified. This is the event code
for BFA events in RXQUE.
XXXX 0628
XXXX 06A8
XXXX 0728
XXXX 0630
XXXX 06B0
XXXX 0730
IBM Processor for Network Resources
DMA QUEUES (DMAQS)
Page 167 of 676
IBM3206K0424