ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 157

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Data Width
DMAQS recognizes 64 bit writes to 64 bit internal registers. DMAQS internal 64-bit registers may be written
either as a 64-bit entity, or by two 32-bit writes. All DMAQS registers are memory mapped on a 64-bit bound-
ary (address bits 2:0 = 0). When in 64-bit addressing mode, an address register is updated with 32 bit writes
(atomicity of update cannot be guaranteed). The user should use semaphores to assure the integrity of the
operation.
Initialization of DMAQS
DMAQS is very simple to set up by following these steps:
pnr25.chapt04.01
August 14, 2000
1. Set up each of the three DMA queues.
2. Set up the queue thresholds if they are being used:
3. Set up the local DMA descriptor range if local descriptors are being used:
4. Set up any options that are being used in the DMAQS Control Register:
5. Finally, clear the diagnostic bit:
6. Need to set up memory bank selection if necessary, but normally Control Memory is used.
To do this, you need to know the size of each queue (see DMAQS Upper Bound Registers on page 159
for choices). Given this information, the DMA queue is set up with two register writes in diagnostic mode
(see DMAQS Control Register on page 164).
The data structure for the DMA queue is now set up.
IBM Processor for Network Resources
DMA QUEUES (DMAQS)
Page 157 of 676
IBM3206K0424