ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 159

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
3.2: DMAQS Upper Bound Registers
These registers specify the encoded size/upper bound of the corresponding DMA queue data structure.
The actual upper bound is calculated by adding the decoded queue size to the lower bound. When the DMA
queue wraps past the upper bound, it wraps back to the lower bound register, thus implementing the DMA
queue as a circular buffer.
Length
Type
Address
Power on Value
Restrictions
pnr25.chapt04.01
August 14, 2000
Bit(s)
2-0
Encoding is as follows:
000
001
010
011
100
101
110
111
59512 bytes of memory
611K bytes of memory
632K bytes of memory
654K bytes of memory
678K bytes of memory
6916K bytes of memory
7132K bytes of memory
7364K bytes of memory
3 bits
Read/Write
Queue 0
Queue 1
Queue 2
X’00000000’
During normal operations, these registers are read only. These registers can only
be written when the diagnostic bit has been set in the DMAQS Control Register.
XXXX 0604
XXXX 0644
XXXX 0684
Description
IBM Processor for Network Resources
DMA QUEUES (DMAQS)
Page 159 of 676
IBM3206K0424