ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 261

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
9.10: POOLS Pointer Queues Length Registers
The POOLS Pointer Queues Length Registers indicates the length of the queue. The bits are a 16-bit count.
A primitive that adds to the queue increments this counter. Primitives that remove items from the queue dec-
rement this counter.
Length
Type
Address
Power on Value
Restrictions
9.11: POOLS Interrupt Enable Register
This register is used to enable bits from the POOLS Status Register and potentially generate interrupts to the
control processor. When both a bit in this register and the corresponding bit(s) in the POOLS Status Register
are set, the POOLS interrupt to PCINT will be enabled.
See Note on Set/Clear Type Registers on page 93 for more details on addressing. See POOLS Status Regis-
ter on page 265 for the bit descriptions.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt04.01
August 14, 2000
16 bits
Read/Write
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets /
Buffer Size 4
X’00 00’
During normal operations, this register is to be used as a read only register. It can be
written when the diagnostic mode bit is set, otherwise the write is ignored. This register
is cleared when the POOLS Pointer Queues DRAM Lower Bound Address Register is
written to.
32 bits
Clear/Set
XXXX 3078 and 07C
X’00 03 F8 00’
None
XXXX 3064
XXXX 3068
XXXX 306C
XXXX 3070
XXXX 3074
IBM Processor for Network Resources
Buffer Pool Management (POOLS)
Page 261 of 676
IBM3206K0424