ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 525

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Sonet Framer Core (FRAMR Chiplet Address Mapping)
FRAMR Chiplet Address Mapping
GPPINT Architecture
Overview
The General Purpose Processor INTerface (GPPINT) provides direct access to registers located in the
GPPINT module; it provides delayed access to registers and counters located in the GppHandler modules of
the various chiplets of the SONET core. GPPINT controls the handshaking with the external microprocessor
as well as the handshaking with the GppHandlers at the asynchronous chiplet interfaces. Address decoding
is done to the chiplet level in GPPINT. In addition, addresses are decoded to the register level for the local
GPPINT registers.
Reset Register
Each chiplet is controlled by one reset bit. At power-on, all reset bits are active and the chiplets are disabled.
They can be released by the General Purpose Processor (GPP) only after all global configuration parameters
have been set and the clocks to the chiplets have been established. In addition, there are reset bits for the
chiplets that do not have their own GppHandler.
Interrupt Registers
The interrupt register is used as a pointer to the chiplet interrupt registers with pending requests: the clock
status error register, and the handshaking error register. An active bit of the interrupt register is reset by
removing the cause for the request in the corresponding chiplet or by masking the active IRQ bit(s) in the
chiplet; therefore, the interrupt registers (including the pointer) are read only. All interrupt and pointer regis-
ters have a corresponding MASK register (R/W). Every unmasked, active interrupt bit causes an active
pointer bit. Every unmasked, active pointer bit causes activation of the interrupt signal to the microprocessor.
pnr25.chapt06.01
August 14, 2000
Chiplet Name
Reserved
Reserved
Reserved
ACH_Rx
OFP_Rx
ACH_Tx
OFP_Tx
GPPINT
Short Name
HR
OR
GP
HT
OT
Chiplet Base Address
X’C00’
X’D00’
X’000’
X’100’
X’200’
X’300’
X’400’
X’800’
Chiplet Address Range
X’C00 - CFF’
X’800 - BFF’
X’D00 - FFF’
X’000 - 0FF’
X’100 - 1FF’
X’200 - 2FF’
X’300 - 3FF’
X’400 - 7FF’
IBM Processor for Network Resources
Number of Bytes
GPPINT Architecture
Page 525 of 676
IBM3206K0424
1024
1024
256
256
256
256
256
768