ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 173

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
3.17: DMAQS Local Descriptor Range Registers
These registers specify the lower and upper bounds respectively of the memory range for local DMA descrip-
tors.
These registers contain the address of the lower and upper bound of the memory range of descriptors that
are in the IBM3206K0424. If a descriptor block is enqueued, it is compared to these registers. If it falls within
this range, only the descriptor address is placed on the queue. When the descriptor is to be loaded into the
DMA registers, and it falls within this range, it will not be taken from the queue but loaded directly from the
descriptor address. These registers are 4K aligned. The upper bound register contains the address of the last
4K block in the local descriptor address range.
Length
Type
Address
Power on Value
Restrictions
3.18: DMAQS Event Queue Number Register
This register specifies which DMAQS queue should be used when DMA descriptors are enqueued from
CSKED (DMA on transmit comp). This register also indicates the RXQUE Event Queue to which events
should be enqueued for each DMAQS queue register.
Length
Type
Address
Power on Value
Restrictions
pnr25.chapt04.01
August 14, 2000
20 bits
Read/Write
XXXX 07CC
X’00002210’
Can be written in diagnostic mode only.
Invalid values (that is, 3), force queue number 2.
Lower Bound
Upper Bound
Read/Write
Lower Bound
Upper Bound
Lower Bound
Upper Bound
Can be written in diagnostic mode only. Upper bound is 32 bits. The upper 32 bits are
internally generated, and are not different from the upper 32 bits of the lower bound reg-
ister. The last four addresses in this range are reserved, and should not be used to hold
descriptors.
64 bits
32 bits
XXXX 0798
XXXX 07A4
X’0000000000000000’
X’00000000’
IBM Processor for Network Resources
DMA QUEUES (DMAQS)
Page 173 of 676
IBM3206K0424