ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 443

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Initializing Packet/Control Memory
The following list shows the steps to use CHKSM to initialize Packet or Control Memory:
Testing Packet/Control Memory
The following list shows the steps to use CHKSM to test packet or Control Memory:
Using Ripple Pattern Generation/Checking in Packet/Control Memory
The procedures to use the ripple pattern generation and checking are the same as using test write/read
modes. The only difference is that the use ripple pattern mode bit must be set and the ripple pattern base
register must be set up.
Running a TCP/IP Checksum in Packet/Control Memory
The following list shows the steps to use CHKSM to generate/verify a TCP/IP checksum:
pnr25.chapt05.01
August 14, 2000
• Make sure CHKSM is in diagnostic mode, and other mode bits are reset
• Set the start address by writing the base address
• Set up the read/write count with number of bytes to initialize
• Set up the test pattern register (ripple pattern register) with pattern to use
• Set up the Control Register to enable test mode, enable checksum entity, and set the memory select bit
• Now busy wait until operation is done (or set up Interrupt Enable Register and wait for interrupt)
• First initialize memory with a pattern using above sequence
• Make sure CHKSM is in diagnostic mode, and other mode bits are reset
• Set the start address by writing the base address
• Set up the read/write count with number of bytes to test (same as initialization value)
• The test pattern register (ripple pattern register) already contains the pattern
• Set up the Control Register to enable test mode, turn on RW bit, enable checksum entity, and set the
• Now busy wait until operation is done (or set up interrupt Enable register and wait for interrupt)
• When done, check the status register for any errors
• Make sure CHKSM is in diagnostic mode (not enabled)
• Set the start address by writing the base address
• Set up the read/write count with number of bytes to run checksum over, and set the upper two bits of the
• Now busy wait until operation is done (or set up interrupt Enable register and wait for interrupt)
correctly based which memory is to be initialized
memory select bit correctly based which memory is to be initialized
read/write count register. Writing these upper two bits assumes other mode bits are set correctly (that is,
memory bank select).
On-chip Checksum and DRAM Test Support (CHKSM)
IBM Processor for Network Resources
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IBM3206K0424