tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 114

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ACK*/READY
SWE*/BWE*
ADDR [19:0]
DATA [31:0]
SYSCLK
CE*/BE*
(Output)
OE*
7.3.7.2
ACK*/READY Input/Output Switching Timing
in the ACK*/Ready Dynamic mode, the ACK*/Ready signal is an input signal when in the
External ACK mode or the Ready mode, but is an output signal in all other modes.
cycle where the CE* signal is asserted. At the end of the access cycle, the ACK* signal is output
(driven) again one clock cycle after the CE* signal is deasserted (see Figure 7.3.3 and Figure
7.5.23).
Figure 7.3.6 SHWT 1 Wait (Normal Mode, Single Read/Write Cycle)
When in the ACK*/Ready Static mode, the ACK*/Ready signal is always an input signal. When
During External ACK mode or Ready mode access, the ACK* signal becomes High-Z at the
7-14
Chapter 7 External Bus Controller
EBCCRn.PWT:WT=0
EBCCRn.SHWT=1