tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 378

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Bit
4:0
7
6
5
Mnemonic
RFDN
RDIS
STIS
Reception Data
Full
Status Change
Reserved
Reception Data
Stage Status
Field Name
Figure 11.4.3 DMA/Interrupt Status Register (2/2)
Receive DMA/Interrupt Status (Default: 0)
This bit is set when valid data of the amount set by the Receive FIFO
Request Trigger Level (RDIL) of the FIFO Control register (SIFCR) is stored
in the Receive FIFO.
Status Change Interrupt Status (Default: 0)
This bit is set when at least one of the interrupt statuses selected by the
Status Change Interrupt Condition field (STIE) of the DMA/Interrupt Control
Register (SIDICR) becomes “1”.
Receive FIFO Data Number (Default: 00000)
This field indicates how many stages of reception data remain in the
Receive FIFO
(0 – 16 stages).
11-18
Description
Chapter 11 Serial I/O Port
Read/Write
R/W0C
R/W0C
R
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