tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 331

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Bit
1:0
4
3
2
Mnemonic
ICAEN
TCAR
LCFG
Target
Configuration
Access Ready
Initiator
Configuration
Access Enable
Load
Configuration
Data Register
Reserved
Field Name
Figure 10.4.41 PCI Controller Configuration Register (3/3)
Target Configuration Access Ready (Default: 0x0/0x1)
Specifies whether to accept PCI access as a target.
PCI controller receives a target access, when this bit is 1 and
PCISTATUS.E2PDONE bit is 1.
Configuration access from the PCI Bus can be accepted during PCI Boot
up after initialization from EEPROM or after each initialization ends. Please
use the software to set this bit after initialization ends. Retry response to
PCI configuration access is performed until this bit is set.
This bit becomes “1” only when in the PCI Boot Mode and the Satellite
Mode. Operation when this bit is set to “1” then reset to “0” is not defined.
1: Responds to PCI target access.
0: Performs a Retry response to PCI target access.
Initiator Configuration Access Enable (Default: 0x1)
Controls initiator PCI configuration access using the G2P Configuration
Address Register (G2PCFGADRS) and the G2P Configuration Data
Register (G2PCFGDATA). This is a diagnostic function.
1: Initiator configuration access is possible.
0: Initiator configuration access is not possible.
Load PCI Configuration Data Register (Default: 0x0)
When a software reset is performed on this bit using the Software Reset bit
(PCICFG.SRST) when this bit is already set, data is loaded to the
Configuration Space Register from the Configuration Data 0/1/2/3 Register.
1: Load from the Configuration Data 0/1/2/3 Register.
0: Load from EEPROM.
10-73
Description
Chapter 10 PCI Controller
Read/Write
R/W
R/W
R/W
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