tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 303

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Bit
7:0
11
10
9
8
Mnemonic
MEM1PD
MEM2PD
TOBFR
TIBFR
Memory 1
Window Prefetch
Disable
Memory 2
Window Space
Prefetch Disable
Target Out-Bound
FIFO Reset
Target In-Bound
FIFO Reset
Reserved
Field Name
Figure 10.4.17 P2G Configuration Register (2/2)
Memory 1 Window Prefetch Disable (Default: 0x0)
Prefetching during a G-Bus Burst Read transfer cycle to the Memory 1
Space is disabled when this bit is set to “1”. PCI Burst Read transactions
are not supported when prefetching is disabled.
Even if the setting of this bit is changed, prefetchable bits in the Base
Address Register of the PCI Configuration Space will not reflect this
change. We recommend using the default setting when the PCI Controller
is in the Satellite mode.
Memory 2 Window Prefetch Disable (Default: 0x1)
Prefetching during a G-Bus Burst Read transfer cycle to the Memory 2
Space is disabled when this bit is set to “1”. PCI Burst Read transactions
are not supported when prefetching is disabled.
Even if the setting of this bit is changed, prefetchable bits in the Base
Address Register of the PCI Configuration Space will not reflect this
change. We recommend using the default setting when the PCI Controller
is in the Satellite mode.
Target Out-Bound FIFO Reset (Default: 0x0)
The PCI Controller flushes the CORE internal Target Out-Bound FIFO
when “1” is written to this bit. This bit always reads out “0” when it is read.
This is a diagnostic function.
Target In-Bound FIFO Reset (Default: 0x0)
The PCI Controller flushes the CORE internal Target In-Bound FIFO when
“1” is written to this bit. This bit always read out “0” when it is read. This is a
diagnostic function.
10-45
Description
Chapter 10 PCI Controller
Read/Write
R/W
R/W
R/W
R/W
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