tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 93

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Reserved
ARBMD
R/W
63:32
30:15
14:0
63
47
31
15
Bit
1
31
5.2.6
30
14
Mnemonic
PRIORITY
ARBMD
⎯
⎯
G-Bus Arbiter Control Register (GARBC)
Reserved
Arbitration
Mode
Reserved
Arbitration
Priority
Field Name
Figure 5.2.6 G-Bus Arbiter Control Register
Specifies how to prioritize G-Bus arbitration.
0 = Fixed priority. The G-Bus arbitration priority conforms to
1 = Round-robin (in a round-robin fashion, PCIC0 > PDMAC >
Note: Before accessing the PCI by DMAC, specify round-robin
Specifies the priority when ARBMD (bit [16]) specifies fixed-
priority mode.
[14:12] = Bus master with the highest priority
[11:9] = Bus master with the second highest priority
[8:6] = Bus master with the third highest priority
[5:3] = Bus master with the fourth highest priority
[2:0] = Reserved (Please do not rewrite.)
000 = PCI controller
001 = PDMAC
010 = DMAC0
011 = DMAC1
A priority of PCIC > PDMAC > DMAC0 > DMAC1 is initially set
up.
the content of the PRIORITY field (bits [14:0]).
DMAC0 > DMAC1 > PCIC1)
as the priority mode. If fixed-priority mode is selected, a
dead lock is likely to occur in PCI bus access.
000_001_010_011_100
Reserved
Reserved
Reserved
PRIORITY
R/W
5-13
Description
⎯
⎯
Chapter 5 Configuration Registers
0xE030
Initial Value Read/Write
1
000_001_01
0_011_100
⎯
⎯
48
32
16
0
R/W
R/W
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
⎯
⎯