tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 415

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.3.6
Memory
14.3.6.1 Overview
Memory
Buffer
Buffer
DMA
DMA
Sample-data Transmission and Reception
wave-data. An overview is described first.
detection and recovery procedure follow. A special case using slot activation control is described last.
This section describes the mechanism for transmission and reception of PCM audio and modem
reception mechanisms.
valid’ bit-fields on the SDIN signal of AC-link.
captures the slot-data.
under control of ACLC Slot Enable Register (ACSLTEN).
prefetched from memory to FIFO through DMA. The received data is buffered on FIFO and then
stored to memory through DMA.
deactivated under control of ACLC Control Enable Register (ACCTLEN).
Write
Data
Read
Data
Figure 14.3.6 and Figure 14.3.7 show conceptual views of the sample-data transmission and
The CODEC requests ACLC to transmit and receive sample-data via ‘slot-request’ and ‘slot-
For transmission, ACLC transmits the data with ‘slot-valid’ tag set. For reception, ACLC
Transmission or reception through each stream can be independently activated or deactivated
ACLC is equipped with a separate FIFO for each data-stream.
Figure 14.3.6 Sample-data Transmission Mechanism
DMAC
Figure 14.3.7 Sample-data Reception Mechanism
DMAC
DMAREQ
DMAREQ
Read
Data
Write
Data
Latch
REQ
Latch
REQ
14-9
In this stage, each DMA is independently activated or
ACCTLEN
ACCTLEN
Strobe
Strobe
The DMA (Direct Memory Access) operation, error
Chapter 14 AC-link Controller
Underrun Error
Overrun Error
ACLC
FIFO
ACLC
FIFO
ACSLTEN
ACSLTEN
Valid Flag
Data
Data
Link-
The data to transmit is
side
Link-
side
Slot Valid,
Slot Data
Slot Valid,
Slot Data
Slot Req
AC-link
AC-link