tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 235

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14:13
Bit
6:5
4:2
15
12
11
10
9
8
7
1
0
Mnemonic
MW
ME
RD
SE
CE
BS
RS
CS
—
—
—
—
Registered DIMM
Master Enable
Slave Enable
Channel Enable
Bank Count
Row Size
Column Size
Memory Width
Field Name
—
—
—
—
Figure 9.4.1 SDRAM Channel Control Register (2/2)
Registered DIMM (Default: 0)
Specifies whether the SDRAM connected to the channel is Registered
memory.
0: Disable Registered memory
1: Enable Registered memory
Reserved
Master Enable (Default: 0)
Specifies during ECC initialization whether a channel will be made the
Master channel.
0: Disable
1: Enable
Slave Enable (Default: 0)
Specifies during ECC initialization whether a channel will be made the
Slave channel.
0: Disable
1: Enable
Enable (Default: 0)
Specifies whether to enable a channel.
0: Disable 1: Enable
Reserved
Number of Banks (Default: 0)
Specifies the bank count.
0: 2 banks
1: 4 banks
Reserved
Row Size (Default: 00)
Specifies the row size.
00: 2048 Rows (11 bits)
01: 4096 Rows (12 bits)
10: 8192 Rows (13 bits)
11: Reserved
Column Size (Default: 000)
Specifies the column size.
000: 256 words (8 bits)
001: 512 words (9 bits)
010: 1024 words (10 bits)
011: 2048 words (11 bits)
100: 4096 words (12 bits)
101-111: Reserved
Reserved
Memory Width (Default: 0)
Specifies the bus width.
0: 64 bits 1: 32 bits
9-19
Description
Chapter 9 SDRAM Controller
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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