tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 193

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

63:24
23:0
Bit
8.4.8
63
47
31
15
Mnemonic
DADINC
DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn)
Offset Address: DMAC0 0xB028 (ch. 0) / 0xB068 (ch. 1) / 0xB0A8 (ch. 2) / 0xB0E8 (ch. 3)
Reserved
Destination
Address
Increment
Field Name
Figure 8.4.8 DMA Destination Address Increment Register
Reserved
DMAC1 0xB828 (ch. 0) / 0xB868 (ch. 1) / 0xB8A8 (ch. 2) / 0xB8E8 (ch. 3)
Destination Address Increment (Default: undefined)
This field sets the increase/decrease value of the DMA Destination
Address Register (DMDARn). This value is a 24-bit two’s complement and
indicates a byte count.
Refer to “8.3.8.1 Channel Register Settings During Dual Address Transfer”
for more information.
DADINC[15:0]
24
Reserved
Reserved
8-37
R/W
⎯
23
Description
Chapter 8 DMA Controller
DADINC[23:16]
R/W
⎯
Read/Write
R/W
48
32
16
0
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value