tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 379

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

31:6
Bit
31
15
5
4
3
2
1
0
11.4.4
Mnemonic
RBRKD
UBRKD
TXALS
OERS
CTSS
TRDY
⎯
Status Change Interrupt Status Register 0 (SISCISR0)
Status Change Interrupt Status Register 1 (SISCISR1)
Reserved
Overrun Error
CTS Status
Receiving Break
Transmission
Data Empty
Transmission
Complete
Break Detected
Field Name
Figure 11.4.4 Status Change Interrupt Status Register
Reserved
Overrun Error Status (Default: 0)
This bit is immediately set to “1” when an overrun error is detected. This bit
is cleared when a “0” is written.
CTS Terminal Status (Default: 0)
This field indicates the status of the CTS signal.
1: The CTS signal is High.
0: The CTS signal is Low.
Receive Break (Default: 0)
This bit is set when a break is detected. This bit is automatically cleared
when a frame that is not a break is received.
1: Current status is Break.
0: Current status is not Break.
Transmit Ready (Default: 1)
This bit is set to “1” if at least one stage in the Transmit FIFO is free.
Transmit All Sent (Default: 1)
This bit is set to “1” if the Transmit FIFO and all transmission shift registers
are empty.
UART Break Detect (Default: 0)
This bit is set when a break is detected. Once set, this bit remains set until
cleared by writing a “0” to it.
Reserved
11-19
6
Description
R/W0C
OERS CTSS
⎯
5
0
Chapter 11 Serial I/O Port
R
4
0
0xF30C (Ch. 0)
0xF40C (Ch. 1)
RBRKD
R
3
0
TRDY TXALS
R
2
1
R
1
1
R/W0C : Type
UBRKD
Read/Write
16
R/W0C
R
R
R
R
R/W0C
0
0
⎯
: Type
: Initial value
: Initial value