tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 231

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

9.3.10.3 Adding Read Latency for Each ECC/Parity Mode
SBErr = Single-bit error
MBErr = Multi-bit error
ECC/Parity Mode
ECC + scrub Mode
Even Parity Mode
Odd Parity Mode
NOP Mode
ECC Mode
EC Mode
ECC/parity mode is selected, whether errors will be generated or not, the error type to be
generated, and whether or not to generate bus errors. Table 9.3.6 shows in cycles the memory
Read access latency that will be added based on NOP mode operation under each condition.
When using the ECC/parity function, memory access latency is added according to which
Table 9.3.6 Read Latency Added for Each ECC/Parity Mode
(ECCCR.MEB)
Notification
Bus Error
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
⎯
No error
SBErr: Do not correct
MBErr: Correct
No error
SBErr: Do not correct
MBErr: Do not correct
No error
SBErr: Correct
MBErr: Do not correct
No error
SBErr: Correct
MBErr: Do not correct
No error
SBErr: Correct & scrub
MBErr: Do not correct
No error
SBErr: Correct & scrub
MBErr: Do not correct
No error
MBErr: Do not correct
No error
MBErr: Do not correct
Error Type/Operation
9-15
⎯
Chapter 9 SDRAM Controller
Added Read Latency
(in cycles)
Max. 22
Max. 22
0
0
0
1
2
1
2
1
2
1
3
1
2
0
0
1
1