tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 320
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tmpr4937
Manufacturer Part Number
tmpr4937
Description
64-bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMPR4937.pdf
(552 pages)
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63:38
35:8
Bit
7:0
37
36
63
47
31
15
10.4.34 G2P I/O Space G-Bus Base Address Register (G2PIOGBASE)
Mnemonic
BA[35:8]
BSWAP
EXFER
Reserved
Byte Swap
Endian Transfer
Base Address
Reserved
Field Name
BA[15:8]
R/W
0x00
Figure 10.4.32 G2P I/O Space G-Bus Address Register
Reserved
Byte Swap Disable
(Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte
swapping of the I/O space.
1: Do not perform byte swapping.
0: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to “1”
when in the Big Endian Mode, the byte order of transfer to the I/O Memory
Space through DWORD (32-bit) access will not change.
Endian Transfer
(Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1)
Sets the Endian Transfer of the I/O Space.
1: Performs Endian Transfer.
0: Does not perform Endian Transfer.
Please use the default state.
Base Address (Default: 0x0_0000_00)
Sets the G-Bus base bus address of the I/O Memory Space for initiator
access.
Can set the base address in 256-byte units.
BA[31:16]
Reserved
8
0x0000
R/W
10-62
7
38
Description
BSWAP
0x0/0x1 0x1/0x0
R/W
37
Chapter 10 PCI Controller
EXFER
R/W
36
Reserved
0x00
R
35
BA[35:32]
R/W
0xD138
0x0
Read/Write
R/W
R/W
R/W
R
48
32
16
0
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
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