tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 384

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

31:8
Bit
7:0
31
15
11.4.9
Mnemonic
RxD
Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0)
Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1)
Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit
(DMCCRn.LE) setting of the DMA Controller.
When using the DMA Controller to perform DMA transmission, set the following addresses in the
•
•
Reserved
Reception Data
Reserved
Field Name
Little Endian:
Big Endian:
Figure 11.4.9 Receive FIFO Register
Receive Data
This field reads reception data from the Receive FIFO.
Reading this register updates the Reception Data Status.
0xF320 (Ch.0), 0xF420 (Ch.1)
0xF323 (Ch.0), 0xF423 (Ch.1)
Reserved
8
11-24
7
Description
Chapter 11 Serial I/O Port
Undefined
RxD
R
16
0
Read/Write
R
: Type
: Initial value
: Type
: Initial value
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