tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 194

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

63:26
25:0
Bit
8.4.9
63
47
31
15
Mnemonic
DMCNTR
DMA Count Register (DM0CNTRn, DM1CNTRn)
Offset Address: DMAC0 0xB018 (ch. 0) / 0xB058 (ch. 1) / 0xB098 (ch. 2) / 0xB0D8 (ch. 3)
Reserved
Reserved
Count
Field Name
DMAC1 0xB818 (ch. 0) / 0xB858 (ch. 1) / 0xB898 (ch. 2) / 0xB8D8 (ch. 3)
Count Register (Default: undefined)
This register sets the byte count that is transferred by the DMA Channel
Register setting. The value is a 26-bit unsigned data that is decremented
only by the size of the data transferred during a single bus operation.
Refer to “8.3.7.1 Channel Register Settings During Single Address
Transfer” and “8.3.8.1 Channel Register Settings During Dual Address
Transfer” for more information.
Figure 8.4.9 DMA Count Register
26
25
DMCNTR[15:0]
Reserved
Reserved
8-38
R/W
⎯
Description
DMCNTR[25:0]
Chapter 8 DMA Controller
R/W
⎯
Read/Write
R/W
48
32
16
0
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value