tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 119

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ACK*/READY
7.3.8
SWE*/BWE*
ADDR [19:0]
DATA [31:0]
SYSCLK
(Input)
ACK*/READY
CE*
SWE*/BWE*
ADDR [19:0]
DATA [31:0]
Clock Options
SYSCLK signal clock frequency can be set to one of the following divisions of the internal bus clock
(GBUSCLK): 1/1, 1/2, 1/3, 1/4. The ADDR[14:13] signal is used to set this frequency during reset, and
the setting is reflected in the SYSCLK Division Ratio field (CCFG.SYSSP) of the Chip Configuration
Register.
bus clock (GBUSCLK) for each channel independent of the SYSCLK signal clock frequency: 1/1, 1/2,
1/3, 1/4. The external signal of the External Bus Controller operates synchronous to this operation
clock. The Bus Speed field (EBCCRn.SP) of the External Bus Channel Control Register sets this
frequency.
SYSCLK signal. If these two values do not match, then the channel, the operation reference clock, and
the SYSCLK signal will no longer be synchronous and will not operate properly.
SYSCLK
External devices connected to the external bus can use the SYSCLK signal as the clock. The
The operation reference clock frequency can be set to one of the following divisions of the internal
Please set the same value as CCFG.SYSSP to EBCCRn.SP when the external device uses the
(Input)
CE*
Figure 7.3.14 Ready Input Timing (Write Cycle)
Start Ready
Check
Acknowledge Ready
7-19
Acknowledge Ready
Chapter 7 External Bus Controller
3 clocks
4 clocks
3 clocks
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
4 clocks
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0