tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 479

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

31:9
Bit
7:4
3:0
8
15.4.13 Interrupt Edge Detection Clear Register (IREDC)
31
15
Mnemonic
EDCE0
EDCS0
⎯
⎯
Edge Detection
Clear Enable 0
Edge Detection
Clear Source 0
Reserved
Field Name
⎯
⎯
Figure 15.4.13 Interrupt Status Control Register
Reserved
Edge Detection Clear Enable 0 (Default: 0)
Clears edge detection of interrupts specified by the EDCS0 field.
0: Does not clear.
1: Clears.
Value always becomes “0” when this bit is read.
Reserved
Edge Detection Clear Source 0 (Default: 0x0)
These bits specify the interrupt source to be cleared.
1111: Reserved
1110: Reserved
1101: Reserved
1100: Reserved
1011: Reserved
1010: Reserved
1001: Reserved
1000: Reserved
0111: External INT [5] interrupt
0110: External INT [4] interrupt
0101: External INT [3] interrupt
0100: External INT [2] interrupt
0011: External INT [1] interrupt
0010: External INT [0] interrupt
0001: Reserved
0000: Reserved
9
EDCE0
RW1C
Reserved
8
0
15-33
7
Explanation
Chapter 15 Interrupt Controller
Reserved
0xF660
4
3
EDCS0
0000
R/W
Read/Write
R/W1C
R/W
16
0
⎯
⎯
: Type
: Default
: Type
: Default