tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 99

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

MASTERCLK
Table 6.1.4 Relationship Among Different Clock Frequencies (for TMPR4937XBG-333, CPUCLK = 333 MHz)
and Boot Configured
Master Clock (Input)
(MHz)
133
6.2
111
33
27
83
20
74
18
† The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10].
-
-
6.2.1
6.2.2
Settings
Boot
Configured
Setting
ADDR[3:0]
HLHL (x10.0)
HLLH (x12.0)
LLHH (x18.0)
HLLL (x16.0)
HHHL (x2.5)
HHLH (x3.0)
HHHH(x2.0)
HLHH(x8.0)
HHLL (x4.0)
LHHH(x4.5)
Power-Down Mode
Halt Mode and Doze Mode
Doze. The TX49/H3 can exit from Halt or Doze mode upon an interrupt exception. Ensure, therefore,
that the TX49/H3 does not enter Halt or Doze mode when all interrupts are masked in the interrupt
controller.
TX4937 does not use the snoop function of the TX49/H3 core, the bit should be set to select Halt mode,
which achieves greater power reduction than Doze mode.
Power Reduction for Peripheral Modules
timers/counters, parallel I/O controller, or AC-link controller, it can stop the input clock for that module
to reduce power dissipation.
module should be reset before its clock can be turned on or off. This reset is performed using the reset
bit for the specific module, provided in the clock control register. The reset also initializes the registers
of the module, thus requiring subsequent setup of necessary register values and other configurations.
Refer to Section 5.2.5, "Clock Control Register" for detail of the clock control register (CLKCTR).
The WAIT instruction causes the TX49/H3 core to enter either of the two low-power modes: Halt and
The HALT bit of the TX49/H3 core Config register is used to select Halt or Doze mode. As the
When the system does not use the DMA controller, PCI controller, serial I/O controller,
The clock control register (CLKCTR) is used to control whether to turn each clock on or off. The
CPUCLK
(MHz)
333
Internal Clock
GBUSCLK
(MHz)
133
111
83
74
-
IMBUSCLK
(MHz)
66
55
41
37
-
SDCLK
[3:0]
(MHz)
133
111
83
74
-
133
111
(1/1)
83
74
HH
Boot Configured Settings
-
SYSCLK (MHz)
6-5
PCIDIVMODE[2:0]
(1/2)
66
55
41
37
HL
-
(1/3)
44
37
27
24
LH
-
External Clock (Output)
(1/4)
33
27
20
18
LL
-
(1/4)
LLH
83
-
(1/4.5)
LHH
74
-
Chapter 6 Clocks
PCICLK[5:0] (MHz) †
HLH
(1/5)
66
PCIDIVMODE[2:0]
-
CCFG Settings
(1/5.5)
HHH
60
-
(1/8)
LLL
41
-
(1/9)
LHL
38
-
(1/10)
HLL
33
-
(1/11)
HHL
30
-