tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 273

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.3.10 PDMAC (PCI DMA Controller)
10.3.9.2 PME* Signal (Satellite Mode)
10.3.9.3 PME* Signal* (Host Mode)
10.3.10.1 DMA Transfer
controller. Data can be transferred bidirectionally between the G-Bus and the PCI Bus.
Note: The PDMAC can only access the SDRAMC on the G-Bus. It does not provide support
The PCI DMA Controller (PDMAC) is a one-channel PCI Director Memory Access (DMA)
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when an external satellite device asserts the PME* signal while the TX4937 is in the Host mode. It
is also possible to generate PME Detection interrupts at this time.
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2.
for access to other controllers on the G-Bus.
The following PMEs (Power Management Events) are reported when in the Satellite mode.
The PME Detection bit (PCICSTATUS.PMED) of the PCI Controller Status Register is set
The following DMA transfer procedure does not use the Chain DMA mode.
The PCI Host device sets the PME_En bit of the PMCSR Register in the TX4937
Configuration space. This makes it possible for the TX4937 to assert the PME* signal.
Then, the PME_En Set bit (P2GSTATUS.PMEES) of the P2G Status Register is set.
Furthermore, it also becomes possible to generate PME_En Set interrupts. The PME_En bit
value can be read from the PME_En bit (PCISSTATUS.PMEEN) of the Satellite Mode PCI
Status Register.
Writing “1” to the PME bit (P2GCFG.PME) of the P2G Configuration Register sets the
PME_Status bit of the PMCSR Register, then asserts the PME* signal, which is the open
drain signal. PME is then reported to the PCI Host device.
The PCI Host device checks the PMCSR PME_Status bit of each PCI device, then specifies
the PCI device that asserted the PME* signal.
After the process corresponding to PME ends, the PCI Host device writes “1” to the TX4937
PME_Status bit that reported PME, thereby reporting the end of the process. As a result, the
PME_Status bit of the PMCSR Register is cleared and the PME* signal is deasserted.
Then, the PME Status Clear bit (P2GSTATUS.PMECLR) of the P2G Status Register is set. It
is also possible to generate PME Status Clear interrupts.
Address Register and Count Register Setting
Sets values for the three following registers.
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Chain Address Register Setting
Sets “0” to the PDMAC Chain Address Register (PDMCA).
PDMAC G-Bus Address Register (PDMGA)
PDMAC PCI Bus Address Register (PDMPA)
PDMAC Count Register (PDMCTR)
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Chapter 10 PCI Controller