tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 118

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ACK*/READY
ACK*/READY (Input)
ADDR [19:0]
DATA [31:0]
SYSCLK
7.3.7.5
(Input)
ADDR [19:0]
OE*
CE*
DATA [31:0]
SYSCLK
OE*
CE*
Ready Input Timing
timing is the same as the ACK* input timing explained in 7.3.7.4 ACK* Input Timing (External
ACK Mode) with the two following exceptions.
•
•
The ACK*/Ready pin is used as a Ready input when in the Ready mode. The Ready input
Ready must be a High Active signal.
When in the Ready mode, the Wait cycle count specified by EBCCRn.PWT:WT must be
inserted in order to delay the Ready signal check (see 7.3.6.3 Ready Mode).
Figure 7.3.13 Ready Input Timing (Read Cycle)
Start Ready
Check
Acknowledge Ready
7-18
Chapter 7 External Bus Controller
Acknowledge Ready
2 clocks
Latch Data
2 clocks
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
Latch Data