tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 192

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

63:24
23:0
Bit
8.4.7
63
47
31
15
Mnemonic
SADINC
DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)
Offset Address: DMAC0 0xB020 (ch. 0) / 0xB060 (ch. 1) / 0xB0A0 (ch. 2) / 0xB0E0 (ch. 3)
Reserved
Source Address
Increment
Field Name
Reserved
Figure 8.4.7 DMA Source Address Increment Register
DMAC1 0xB820 (ch. 0) / 0xB860 (ch. 1) / 0xB8A0 (ch. 2) / 0xB8E0 (ch. 3)
Source Address Increment (Default: undefined)
This field sets the increase/decrease value of the DMA Source Address
Register (DMSARn). This value is a 24-bit two’s complement and indicates
a byte count.
Refer to “8.3.7.1 Channel Register Settings During Single Address
Transfer” and “8.3.8.1 Channel Register Settings During Dual Address
Transfer” for more information.
SADINC[15:0]
24
Reserved
Reserved
8-36
R/W
⎯
23
Description
Chapter 8 DMA Controller
SADINC[23:16]
R/W
⎯
Read/Write
R/W
48
32
16
0
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value