tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 239

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

63:56
55:48
47:32
31:24
23:17
15:11
15
63
31
47
0
Bit
16
10
9
9.4.4
Mnemonic
0
MDLNO
VERNO
DECC
MEB
Reserved
MEI
DM
—
—
—
ECC Control Register (ECCCR)
0
Model Number
Version Number
Diagnostic ECC
Diagnostic Mode
Multi-Bit Error
Bus Error Enable
Multi-Bit Error
Interrupt Enable
0
MDLNO
Field Name
DECC
0x10
R/W
—
—
—
11
0
MEB
R/W
10
0
0
Figure 9.4.4 ECC Control Register (1/2)
Model Number (Default: 0x10)
Indicates the model number. The default value for the TX4937 is 0x10.
This field is Read Only.
Address Mask (Default: 0x10)
Indicates the version number. The default value for the TX4937 is 0x10.
This field is Read Only.
Reserved
Diagnostic ECC (Default: 0x00)
The value set by this field is output from CB[7:0] as the check code when
the DM bit is set to “Enable.”
Reserved
ECC Diagnostic Mode (Default: 0)
Specifies whether to use the Diagnostic Mode.
0: Disable
1: Enable
Reserved
Multi-Bit Error Bus Error Enable (Default: 0)
Specifies whether to generate a bus error when a multi-bit error occurs.
When this function is enabled, an NMI is generated for RMW* errors
occurring during a Write operation to the TX49/H3 core. Bus errors are
generated for all other operations.
0: Disable
1: Enable
Multi-Bit Error Interrupt Enable (Default: 0)
Specifies whether to generate an interrupt during a multi-bit error.
0: Disable
1: Enable
R/W
MEI
9
0
0
R/W
SEI
56
24
Reserved
0
8
0
9-23
55
23
7
Description
Chapter 9 SDRAM Controller
0xA000
Reserved
Reserved
VERNO
0x10
17
1
ECCE
R/W :Type
R/W :Type
DM
48
32
16
Read/Write
0
0
0
R
R
R/W
R/W
R/W
R/W
:Initial value
:Type
:Initial value
:Initial value
:Type
:Initial value
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