tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 115

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7.3.7.3
ACK*/READY
ACK*/READY
SWE*/BWE*
ADDR [19:0]
ADDR [19:0]
DATA [31:0]
DATA [31:0]
ACK* Output Timing (Normal Mode, Page Mode)
signal becomes an output signal and is asserted for one clock cycle to send notification to the
external device of the data Read and data Write timing.
ACK* signal is asserted. (See Figure 7.3.7 ACK* Output Timing (Single Read Cycle)).
signal is deasserted, and the data is held for one more clock cycle after that. (See Figure 7.3.8
ACK* Output Timing (Single Write Cycle)).
(Output)
SYSCLK
SYSCLK
(Output)
When in the Normal mode and Page mode of the ACK*/Ready Dynamic mode, the ACK*
During the Read cycle, the data is latched at the rise of the next clock cycle after when the
During the Write cycle, SWE*/BWE* is deasserted at the next clock cycle after when the ACK*
OE*
CE*
CE*
Figure 7.3.7 ACK* Output Timing (Single Read Cycle)
Figure 7.3.8 ACK* Output Timing (Single Write Cycle)
7-15
Chapter 7 External Bus Controller
Data is latched
1 clock
2 clocks
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0