tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 6

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7. External Bus Controller .......................................................................................................................................... 7-1
8. DMA Controller...................................................................................................................................................... 8-1
6.3
7.1
7.2
7.3
7.4
7.5
7.6
8.1
8.2
8.3
8.4
6.2.2
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.4.1
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.3.14
8.3.15
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
Power-On Sequence ....................................................................................................................................... 6-6
Features .......................................................................................................................................................... 7-1
Block Diagram ............................................................................................................................................... 7-2
Detailed Explanation...................................................................................................................................... 7-3
Register ........................................................................................................................................................ 7-20
Timing Diagrams ......................................................................................................................................... 7-24
Flash ROM, SRAM Usage Example ........................................................................................................... 7-54
Features .......................................................................................................................................................... 8-1
Block Diagram ............................................................................................................................................... 8-2
Detailed Explanation...................................................................................................................................... 8-4
DMA Controller Registers ........................................................................................................................... 8-23
Power Reduction for Peripheral Modules............................................................................................ 6-5
External Bus Control Register ............................................................................................................. 7-3
Global/Boot-up Options....................................................................................................................... 7-4
Address Mapping................................................................................................................................. 7-5
External Address Output...................................................................................................................... 7-6
Data Bus Size....................................................................................................................................... 7-7
Access Mode........................................................................................................................................ 7-9
Access Timing ................................................................................................................................... 7-13
Clock Options .................................................................................................................................... 7-19
External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1)
0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7)...... 7-21
ACE* Signal ...................................................................................................................................... 7-25
Normal mode access (Single, 32-bit Bus).......................................................................................... 7-27
Normal mode access (Burst, 32-bit Bus) ........................................................................................... 7-31
Normal Mode Access (Single, 16-bit bus) ......................................................................................... 7-33
Normal Mode Access (Burst, 16-bit Bus).......................................................................................... 7-37
Normal Mode Access (Single, 8-bit Bus) .......................................................................................... 7-39
Normal Mode Access (Burst, 8-bit Bus)............................................................................................ 7-42
Page Mode Access (Burst, 32-bit Bus) .............................................................................................. 7-44
External ACK Mode Access (32-bit Bus) .......................................................................................... 7-46
READY Mode Access (32-bit Bus) ................................................................................................... 7-52
Transfer Mode...................................................................................................................................... 8-4
On-chip Registers ................................................................................................................................ 8-5
External I/O DMA Transfer Mode ....................................................................................................... 8-5
Internal I/O DMA Transfer Mode ........................................................................................................ 8-8
Memory-Memory Copy Mode............................................................................................................. 8-9
Memory Fill Transfer Mode ................................................................................................................ 8-9
Single Address Transfer ....................................................................................................................... 8-9
Dual Address Transfer ....................................................................................................................... 8-12
DMA Transfer.................................................................................................................................... 8-17
Chain DMA Transfer ......................................................................................................................... 8-18
Dynamic Chain Operation ................................................................................................................. 8-20
Interrupts............................................................................................................................................ 8-21
Transfer Stall Detection Function ...................................................................................................... 8-21
Arbitration Among DMA Channels ................................................................................................... 8-22
Restrictions in Access to PCI Bus...................................................................................................... 8-22
DMA Master Control Register (DM0MCR, DM1MCR)................................................................... 8-25
DMA Channel Control Register (DM0CCRn, DM1CCRn) .............................................................. 8-27
DMA Channel Status Register (DM0CSRn, DM1CSRn)) ................................................................ 8-31
DMA Source Address Register (DM0SARn, DM1SARn) ................................................................ 8-33
DMA Destination Address Register (DM0DARn, DM1DARn)........................................................ 8-34
DMA Chain Address Register (DM0CHARn, DM1CHARn) ........................................................... 8-35
DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)............................................. 8-36
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