tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 387

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

12.3 Detailed Explanation
12.3.1
12.3.2
Divide
Rate
128
256
16
32
64
2
4
8
Overview
modes.
(1) Interval Timer Mode (Timer 0, 1, 2)
(2) Pulse Generator Mode (Timer 0, 1)
(3) Watchdog Timer Mode (Timer 2)
Counter Clock
1/256 of the internal clock (IMBUSCLK) frequency, or can be selected from nine counter input signal
(TCLK) types. Divide Register n (TMCCDRn) and the Counter Clock Select bit (TMTCRn.CCS) are
used to select the counter clock. In this situation, IMBUSCLK is the internal clock signal which is the
G-Bus clock divided by 2. See “Chapter 6 Clocks” for more information.
external events. The External Clock Edge bit (TMTCRn.ECES) can be used to select the clock
rising/falling count.
IMBUSCLK = 60 MHz). The following tables shows example count times when using 60 MHz or 66
MHz IMBUSCLK.
The TX4937 has an on-chip 3-channel 32-bit timer/counter. Each channel supports the following
The clock used for counting can be set to a frequency that is 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, or
The counter input signal (TCLK) is used by three channels. Using TCLK makes it possible to count
Set the TCLK clock frequency to 45% or less of IMBUSCLK (TCLK = 27 MHz or less when
TMCCDRn.
This mode periodically generates interrupts.
This is the pulse signal output mode.
This mode is used to monitor system abnormalities.
CCD
000
001
010
011
100
101
110
111
Table 12.3.1 Divide Value and Count (IMBUSCLK = 60 MHz)
Frequency (Hz)
Counter Clock
937.5 K
468.8 K
234.4 K
30.0 M
15.0 M
3.75 M
7.5 M
1.9 M
Resolution (ns)
12-3
1066.67
2133.33
4266.67
133.33
266.67
533.33
33.33
66.67
Max. Set Time
Chapter 12 Timer/Counter
(sec.)
18325.20
1145.32
2290.65
4581.30
9162.60
143.17
286.33
572.66
TMCPRAn Value
for 1 sec.
30000000
15000000
7500000
3750000
1875000
937500
468750
234375