tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 121

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

63:48
47:22
21:20
19:18
Bit
63
47
31
15
7.4.1
111(~D[4])/0000
Mnemonic
BA[35:20]
D[ ] represents the corresponding Data[ ] signal value when the RESET* signal is deasserted. A[ ] represents
the corresponding ADDR[ ] signal value when the RESET* signal is deasserted.
BSZ
R/W
PM
WT
Only in the case of Channel 0 are fields with different defaults in the “Channel 0/Other channel” state.
External Bus Channel Control Register (EBCCRn)
Global/Boot-up Options). Channels 1 - 7 have the same register configuration as Channel 0, but they
have different defaults than Channel 0.
the high-order 32-bit portion of the register must be written first, followed by the Master Enable bit in
the low-order 32-bit portion.
Channel 0 can be used as Boot memory. Therefore, the default is set by the Boot signal (see 7.3.2
When the EBCCRn is programmed using a sequence of 32-bit store instructions, the base address in
Base Address
Reserved
Bus Width
Page Mode
Page Size
Field Name
12
Figure 7.4.1 External Bus Channel Control Register (1/3)
11
Reserved
0
0
External Bus Control Base Address (Default: 0x01FC/0x0000)
A physical address is used to specify the base address. The upper 16 bits
[35:20] of the physical address are compared to the value of this field.
External Bus Control Bus Size (Default: DATA[1:0]/00)
Specifies the memory bus width.
00: Reserved
01: 32-bit width
Note: DATA[1:0] is set to Channel 0 as the default.
External Bus Control Page Mode Page Size (Default: 00)
Specifies the Page mode (Page mode memory support) use and page size.
00: Normal mode
01: 4-page mode
10: 8-page mode
11: 16-page mode
R/W
CS
1 / 0
0x01FC/0x0000
BA[35:20]
Reserved
8
0
R/W
D[5]/0
7-21
R/W
BC
7
10: 16-bit width
11: 8-bit width
RDY
R/W
Chapter 7 External Bus Controller
22
6
0
Description
21
D[1:0]/00
5
A[7:6]/00
BSZ
R/W
R/W
SP
20
4
0x9010 (ch. 2), 0x9018 (ch. 3)
0x9020 (ch. 4), 0x9028 (ch. 5)
0x9030 (ch. 6), 0x9038 (ch. 7)
0x9000 (ch. 0), 0x9008 (ch. 1)
A[8]/0
R/W
ME
19
3
0
R/W
PM
18
0
2
0
SHWT
R/W
17
0
11/00
PWT
R/W
Read/Write
R/W
R/W
R/W
48
32
16
0
0
⎯
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
:Type