tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 236

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

1
2
R/W
63:34
33:32
31:29
28:27
DA
47
15
63
31
t
t
1
1
Bit
26
25
CK
RC
t
RP
is used during (i) refresh cycle time, (ii) single Read, (iii) two transfer burst Reads. The bank cycle time is t
= Clock cycle
9.4.2
+ 1t
SWB
R/W
R/W
BC
14
Mnemonic
0
1
CK
RCD
ACP
DIA
if t
BC
PT
—
13
RAS
29
Reserved
1
SDRAM Timing Register (SDCTR)
+ t
RP
Write Active
Period
Active Command
Time
Precharge Time
RAS-CAS Delay
28
12
Bank Cycle Time
1
Field Name
< t
ACP
R/W
RC
—
27
11
in the case of (ii) (iii).
1
R/W
PT
Figure 9.4.2 SDRAM Timing Register (1/2)
26
1
Reserved
Data In to Active(t
Specifies the period from the last Write data to the Active command.
00: Reserved
01: 4 t
10: 5 t
11: 6 t
Bank Cycle Time (t
Specifies the bank cycle time.
000: 5 t
001: 6 t
010: 7 t
011: 8 t
Active Command Period (t
Specifies the active command time.
00: 3 t
01: 4 t
10: 5 t
11: 6 t
Precharge Time (t
Specifies the precharge time.
0: 2 t
1: 3 t
RAS to CAS Delay (t
Specifies the RAS - CAS delay.
0: 2 t
1: 3 t
RCD
R/W
25
Reserved
1
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
1
100: 9 t
101: 10 t
110: Reserved
111: Reserved
ACE
R/W
24
Reserved
0
DAL
RP
PDAE
CK
RC
R/W
9-20
CK
23
0
) (Default: 1)
RCD
) (Default: 11)
) (Default: 101)
) (Default: 1)
RAS
22
0
2
0x30C
Description
) (Default: 11)
R/W
RP
Chapter 9 SDRAM Controller
0
0x8040
R/W
RC
0
0
34
18
0
CASL
R/W
33
17
1
1
R/W
DIA
DRB
R/W :Type
32
48
16
Read/Write
1
0
0
R/W
R/W
R/W
R/W
R/W
RAS
:Type
:Initial value
:Type
:Initial value
:Initial value
:Type
:Initial value
⎯
+