EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 108

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 24. Motorola Bus Mode Read States
PS019209-0504
STATE S0
STATE S1
STATE S2
STATE S3
STATE S4
STATE S5
The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
On the rising edge of state S2, the CPU asserts AS and DS.
During state S3, no bus signals are altered.
During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
signal. If the termination signal is not asserted at least one full CPU clock period prior to
the rising clock edge at the end of S4, the CPU inserts WAIT (T
asserted. Each wait state is a full bus mode cycle.
During state S5, no bus signals are altered.
Figure 16. Motorola Bus Mode Signal and Pin Mapping
During Write operations, the Motorola bus mode employs 8 states—S0, S1, S2,
S3, S4, S5, S6, and S7—as described in Table 24.
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
RD
P R E L I M I N A R Y
Bus Mode
Controller
Motorola Bus
Signal Equvalents
AS
DS
R/W
DTACK
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
WAIT
Chip Selects and Wait States
Product Specification
) states until DTACK is
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