EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 311
EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 311 of 396
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Figure 57. ZDI Block Data Write Timing
Figure 58. ZDI Single-Byte Data Read Timing
PS019209-0504
ZDA
ZCL
ZDI Read Operations
ZDA
ZCL
ZDI Address
ZDI Address
lsb of
A0
7
ZDI Single-Byte Read
Single-byte Read operations are initiated in the same manner as single-byte Write
operations, with the exception that the R/W bit of the ZDI register address is set to
1. Upon receipt of a slave address with the R/W bit set to 1, the eZ80F91 device’s
ZDI block loads the selected data into the shifter at the beginning of the first cycle
following the single-bit data separator. The most-significant bit (msb) is shifted out
first. Figure 58 illustrates the timing for ZDI single-byte Read operations.
lsb of
ZDI Block Read
A block Read operation is initiated in the same manner as a single-byte Read;
however, the ZDI master continues to clock in the next byte from the ZDI slave as
the ZDI slave continues to output data. The ZDI register address counter incre-
A0
7
Write
8
Read
Byte Separator
8
Byte Separator
Single-Bit
Single-Bit
0/1
9
0/1
9
of DATA
of DATA
Byte 1
msb
D7
msb
D7
1
1
D6
P R E L I M I N A R Y
D6
2
2
D5
3
D5
3
ZDI Data Byte
D4
ZDI Data Bytes
4
D1
7
of DATA
D3
Byte 1
5
D0
lsb
8
Byte Separator
Single-Bit
D2
6
0/1
9
D1
7
D7
Product Specification
1
of DATA
D0
lsb
ZiLOG Debug Interface
8
of DATA
Byte 2
START Signal
End of Data
msb
or New ZDI
D6
2
eZ80F91 MCU
1
9
1
9
292
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