EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 160
EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
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PS019209-0504
Timer Interrupt Identification Register
The TImer x Interrupt Identification Register, detailed in Table 56, is used to flag
timer events so that the CPU can determine the cause of a timer interrupt. This
register is cleared by a CPU Read.
Table 56. Timer Interrupt Identification Register
(TMR0_IIR = 0062h, TMR1_IIR = 0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h)
Bit
Reset
CPU Access
Note: R = Read only;
Bit
Position
7
6
OC3
5
OC3
4
OC1
3
OC0
2
ICB
1
ICA
0
EOC
Value
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Unused.
Output compare, OC3, does not occur.
Output compare, OC3, occurs.
Output compare, OC2, does not occur.
Output compare, OC2, occurs.
Output compare, OC1, does not occur.
Output compare, OC1, occurs.
Output compare, OC0, does not occur.
Output compare, OC0, occurs.
Input capture, ICB, does not occur.
For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICB, occurs.
For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICA, or PWM power trip does not occur.
For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.
Input capture, ICA, or PWM power trip occurs.
For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.
End-of-count does not occur.
End-of-count occurs.
P R E L I M I N A R Y
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
Programmable Reload Timers
Product Specification
R
2
0
eZ80F91 MCU
R
1
0
R
0
0
141
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