EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 328

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See Table
201.
Table 201. ZDI Bus Control Register
(ZDI_BUS_STAT = 17h in the ZDI Register Read Only Address Space)
ZDI Read Memory Register
When a Read is executed from the ZDI Read Memory register, the eZ80F91
device fetches the data from the memory address currently pointed to by the Pro-
gram Counter, PC; the Program Counter is then incremented. In Z80 MEMORY
mode, the memory address is {MBASE, PC[15:0]}. In ADL MEMORY mode, the
memory address is PC[23:0]. Refer to the eZ80 CPU User Manual (UM0077),
available on zilog.com, for more information regarding Z80 and ADL MEMORY
modes. The Program Counter, PC, increments after each data Read. However,
the ZDI register address does not increment automatically when this register is
accessed. As a result, the ZDI master can read any number of data bytes out of
memory via the ZDI Read Memory register. See Table 202.
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
ZDI_BUSACK_EN
6
ZDI_BUS_STAT
[5:0]
Value
0
1
0
1
000000
P R E L I M I N A R Y
R
7
0
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge
signal, BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK
pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
Reserved.
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
R
ZiLOG Debug Interface
2
0
eZ80F91 MCU
R
1
0
R
0
0
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