EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 209
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EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 209 of 396
- Download datasheet (5Mb)
PS019209-0504
Note:
The UARTx_BRG_L registers share the same address space with the
UARTx_RBR and UARTx_THR registers. The UARTx_BRG_H registers share
the same address space with the UARTx_IER registers. Bit 7 of the associated
UART Line Control register (UARTx_LCTL) must be set to 1 to enable access to
the BRG registers.
Table 94. UART Baud Rate Generator Register—Low Bytes
(UART0_BRG_L = 00C0h, UART1_BRG_L = 00D0h)
Table 95. UART Baud Rate Generator Register—High Bytes
(UART0_BRG_H = 00C1h, UART1_BRG_H = 00D1h)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:0]
UART_BRG_L
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:0]
UART_BRG_H
Value
00h–
FFh
Value
00h–
FFh
R/W
R/W
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UART_BRG_H, UART_BRG_L}.
Description
These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UART_BRG_H, UART_BRG_L}.
P R E L I M I N A R Y
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
Universal Asynchronous Receiver/Transmitter
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
Product Specification
R/W
R/W
2
0
2
0
eZ80F91 MCU
R/W
R/W
1
1
1
0
R/W
R/W
0
0
0
0
190
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