EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 232
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EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 232 of 396
- Download datasheet (5Mb)
PS019209-0504
SPI Flags
SPI Baud Rate Generator
Mode Fault
The Mode Fault flag (MODF) indicates that there can be a multimaster conflict in
the system control. The MODF bit is normally cleared to 0 and is only set to 1
when the master device’s SS pin is pulled Low. When a mode fault is detected,
the following sequence occurs:
1. The MODF flag (SPI_SR[4]) is set to 1.
2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0.
3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into
4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI
Clearing the Mode Fault flag is performed by reading the SPI Status register. The
other SPI control bits (SPI_EN and MASTER_EN) must be restored to their origi-
nal states by user software after the Mode Fault flag is cleared to 0.
Write Collision
The write collision flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made to
write to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs.
Clearing the WCOL bit is performed by reading SPI_SR with the WCOL bit set to
1.
The SPI’s Baud Rate Generator creates a lower frequency clock from the high-fre-
quency system clock. The Baud Rate Generator output is used as the clock
source by the SPI.
Baud Rate Generator Functional Description
The SPI’s Baud Rate Generator consists of a 16-bit downcounter, two 8-bit regis-
ters, and associated decoding logic. The Baud Rate Generator’s initial value is
defined by the two BRG Divisor Latch registers {SPI_BRG_H, SPI_BRG_L}. At
the rising edge of each system clock, the BRG decrements until it reaches the
value
value from {SPI_BRG_H, SPI_BRG_L) and outputs a pulse to indicate the end of
the count.
SLAVE mode.
interrupt is generated.
0001h
. On the next system clock rising edge, the BRG reloads the initial
P R E L I M I N A R Y
Product Specification
Serial Peripheral Interface
eZ80F91 MCU
213
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