EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 75

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
PS019209-0504
Table 4. Clock Peripheral Power-Down Register 1
(CLK_PPD1 = 00DBh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
GPIO_D_OFF
6
GPIO_C_OFF
5
GPIO_B_OFF
4
GPIO_A_OFF
3
SPI_OFF
2
I2C_OFF
1
UART1_OFF
0
UART0_OFF
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
R/W
System clock to GPIO Port D is powered down.
Port D alternate functions do not operate correctly.
System clock to GPIO Port D is powered up.
System clock to GPIO Port C is powered down.
Port C alternate functions do not operate correctly.
System clock to GPIO Port C is powered up.
System clock to GPIO Port B is powered down.
Port B alternate functions do not operate correctly.
System clock to GPIO Port B is powered up.
System clock to GPIO Port A is powered down.
Port A alternate functions do not operate correctly.
System clock to GPIO Port A is powered up.
System clock to SPI is powered down.
System clock to SPI is powered up.
System clock to I
System clock to I
System clock to UART1 is powered down.
System clock to UART1 is powered up.
System clock to UART0 and IrDA endec is powered down.
System clock to UART0 and IrDA endec is powered up.
P R E L I M I N A R Y
7
0
R/W
6
0
R/W
2
2
5
0
C is powered down.
C is powered up.
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
Low Power Modes
eZ80F91 MCU
R/W
1
0
R/W
0
0
56

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