EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 143

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Watch-Dog Timer Registers
RESET Or NMI Generation
A WDT time-out causes a RESET or sends a nonmaskable interrupt (NMI) signal
to the CPU. The default operation is for the WDT to cause a RESET.
If the NMI_OUT bit in the WDT_CTL register is set to 0, then upon a WDT time-
out, the RST_FLAG bit in the WDT_CTL register is set to 1. The RST_FLAG bit
can be polled by the CPU to determine the source of the RESET event.
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the
WDT asserts an NMI for CPU processing. The NMI_FLAG bit can be polled by the
CPU to determine the source of the NMI event.
Watch-Dog Timer Control Register
The Watch-Dog Timer Control register, detailed in Table 48, is an 8-bit Read/Write
register used to enable the Watch-Dog Timer, set the time-out period, indicate the
source of the most recent RESET or NMI, and select the required operation upon
WDT time-out.
The default clock source for the Watch-Dog Timer is the WDT oscillator
(WDT_CLK =
be selected. The power-up sequence of the WDT oscillator takes approximately
20 ms.
Table 48. Watch-Dog Timer Control Register
(WDT_CTL = 0093h)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
WDT_EN
6
NMI_OUT
10b
Value Description
0
1
0
1
). To power-down the WDT oscillator, another clock source must
R/W
WDT is disabled.
WDT is enabled. When enabled, the WDT cannot be disabled
without a RESET.
WDT time-out resets the CPU.
WDT time-out generates a nonmaskable interrupt (NMI) to the
CPU.
P R E L I M I N A R Y
7
0
R/W
6
0
0/1
R
5
R
4
0
R/W
3
1
Product Specification
R/W
2
0
eZ80F91 MCU
Watch-Dog Timer
R/W
1
0
R/W
0
0
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