EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 252

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
The I
generate an interrupt at this point). After the next byte of the address (I2C_XSAR)
is received, the I
I2C_SAR[2:1] are used as the upper 2 bits for the 10-bit extended address. The
full 10-bit address is supplied by {I2C_SAR[2:1], I2C_XSAR[7:0]}. See Table 125.
Table 125. I
(I2C_XSAR = 00C9h)
I
This register contains the data byte/slave address to be transmitted or the data
byte just received. In TRANSMIT mode, the most-significant bit of the byte is
transmitted first. In RECEIVE mode, the first bit received is placed in the most-sig-
nificant bit of the register. After each byte is transmitted, the I2C_DR register con-
tains the byte that is present on the bus in case a lost arbitration event occurs.
See Table 126.
Table 126. I
(I2C_DR = 00CAh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SLAX
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
DATA
2
C Data Register
2
C sends an ACK after receiving the I2C_XSAR byte (the device does not
2
2
C Extended Slave Address Register
C Data Register
2
C generates an interrupt and enters SLAVE mode.Then
Value Description
00h–
FFh
Value Description
00h–
FFh
R/W
R/W
Least-significant 8 bits of the 10-bit extended slave address.
I
P R E L I M I N A R Y
7
0
7
0
2
C data byte.
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
Product Specification
R/W
R/W
2
0
2
0
I
2
C Serial I/O Interface
eZ80F91 MCU
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
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