EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 175

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Figure 33. PWM Nonoverlapping Output Delay
PS019209-0504
System Clock
TMR3_Count
Clock Enable
Note:
PWM0
PWM0
counter, such that a setting of 0000b represents a delay of 0 system clock peri-
ods, and a setting of 1111b represents a delay of 15 system clock periods. The
PWM delay feature is illustrated in Figure 33, with associated addressing listed in
Table 72.
The PWM nonoverlapping delay time must always be defined to be less than the
delay between the rising and falling edges (and the delay between the falling and
rising edges) of all Multi-PWM outputs. In other words, a rising (falling) edge can-
not be delayed beyond the time at which it is subsequently scheduled to fall (rise).
Table 72. PWM Nonoverlapping Output Addressing
Parameter
Timer clock is SCLK ÷ 4
Timer reload value
PWM0 rising edge
PWM0 falling edge
Prescaler divider = 4
PWM nonoverlapping delay = 3
PWM enable
PWM0 enable
Multi-PWM enable
A
9
8
P R E L I M I N A R Y
7
Control Register(s)
TMR3_CTL[CLK_DIV]
{TMR3_RR_H, TMR3_RR_L}
{TMR3_PWM0R_H, TMR3_PWM0R_L}
{TMR3_PWM0F_H, TMR3_PWM0F_L}
TMR3_CTL[CLK_DIV]
TMR3_PWM_CTL2[PWM_DLY]
TMR3_PWM_CTL1[PAIR_EN]
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[MPWN_EN]
3 x SCLK
6
5
4
Programmable Reload Timers
3
Product Specification
3 x SCLK
2
eZ80F91 MCU
Value
00b
000Ch
0008h
0004h
00b
0011b
1
1
1
1
C
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